1. Field of the Invention
The invention relates to a transistor structure, specifically a self-aligned channel transistor, and a process for forming a self-aligned channel transistor.
2. Description of the Related Art
With the continuing quest to define and produce transistors having ever-smaller overall cell geometries that are capable of operating at increasing switching speeds, many variations on the conventional self aligned channel region have been attempted. For the purposes of this application, cell geometry is defined as the two-dimensional surface area required for implementing a single, integral active lodging element, typically an N- or P-channel resistor or a pair of complementary transistors. Cell geometry can be distinguished from transistor geometry in that the latter refers to the three-dimensional structure of a single integral logic element.
A great deal of time and effort has been spent on producing the so-called LIGHTLY DOPED DRAIN-SOURCE (LDD) semiconductor device, wherein shallow extension regions at the gate oxide/substrate interface closest to the point within the transistor where a large degree of electric field strength occurs. Typically, these extension regions are provided adjacent to the source or drain (referred to collectively herein as the "active" regions) in a typical semiconductor device.
The typical LDD structure involves providing narrow, self-aligned--lightly-doped regions between the device channel and more heavily doped source-drain diffusions in the device. It has been repeatedly shown that significant improvement in breakdown voltages, hot electron effects, and short channel threshold effects can be achieved using LDD regions, thereby allowing transistor operation at higher voltages and shorter channel lengths. Indeed, LDD technology is extremely advantageous in sub-micron channel length devices.
Typical devices constructed with LDD regions are shown in Ogura, et al. titled "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE publication, copyright 1980, and U.S. Pat. Nos. 5,257,095, 4,590,663, 4,282,648, and 4,366,613.
Angled implantation has been attempted as a solution to forming shorter channel length devices.
In the quarter-micron regime, asymmetric n-channel MOSFET devices have been proposed to achieve high current drive-ability and hot-carrier reliability. In a paper by Odanaka, et al., entitled "Potential Design and Transport Property of 0.1-.mu.m MOSFET with Asymmetric Channel Profile," IEEE Transactions on Electron Devices, Vol. 44, No. 4(April 1997), the authors describe the exploration of the relationship between device performance and transport property of a 0.1 .mu.m n-channel MOSFET with an asymmetric channel profile through Monte Carlo device simulations and measured electrical characteristics.
The experimental device taught therein has a gate oxide thickness of 4 nanometers and a polysilicon gate height of 200 nanometers. Processing of the device is equivalent to that of a conventional symmetrical device, except that the V.sub.t channel implant, which is utilized to adjust the threshold voltage of the device, is performed by a threshold adjustment implantation with an orientation non-normal to the surface of the substrate after gate electrode formation. For such a channel implant, an 80 KeV BF2 ion dose of 1.times.10.sup.13 cm-2 is implanted with a tilt angle of 7.degree.. Of note is that this implant is on the source side only of the devices, and no masking of the device during the V.sub.t implant is discussed. The reference teaches that the asymmetry of the lateral channel profile becomes weak as the BF2 energy decreases. After gate electrode formation, arsenic ions with a dose of 1.times.10.sup.14 cm-2 were implanted at an energy of 10 KeV to form shallow source/drain extensions. Subsequently, deep source/drain regions are formed with a high arsenic dose of 6.times.10.sup.15 cm-2 at an energy of 40 KeV, followed by a rapid thermal anneal at 1,050.degree. C. for ten seconds.
In a symmetrical short channel MOSFET, a number of implants are used to control the V.sub.t threshold voltage. In particular, a substrate will typically have formed thereon an epitaxial silicon layer overlying the bulk silicon layer of the semiconductor substrate.
A shallow implant of, for example, a P-type impurity such as boron or BF.sub.2 will be implanted into the channel region wherein the device is to be formed. The energy of the implant will be in a range of about 10-30 KeV to a depth of about 100 .mu.m.
Subsequently, a punch-through stop implant at an energy of about 40-100 KeV to a junction depth of about 0.25 .mu.m will be made into the epitaxial silicon. This pushes dopants further down into the substrate and increases the resistance of the channel.
Finally, a third, approximately 200 KeV implant may be used in addition to form a deep punch-through stop implant for the symmetrical channel device.
Another alternative has been attempted in co-pending application (Ser. No. 08/481,895, U.S. Pat. No. 5,935,867, inventors Alvis, Luning, and Griffin) wherein a process for forming a shallow doped region in a semiconductor device is disclosed. The device includes active regions, such as a source and a drain region provided in a semiconductor substrate, and the shallow doped region may comprise a lightly doped drain region. The method comprises implanting into the substrate a source and a drain region about the gate structure at an angle greater than 0 degrees with respect to the surface normal to the substrate. In this application the angled implant is designed to be on one side of the gate and penetrate the gate to allow for a varied implant region on the other side of the implant.
Angled implants on both sides of the gate structure are demonstrated in U.S. Pat. No. 5,466,957 issued to Yuki, et al. Yuki et al. uses standard well implants (three total) to achieve lighter channel doping by counter-doping the channel region with an impurity having a conductivity opposite to that of the channel. This approach may be good in the case of hot carrier injection problems but has the consequence of degrading mobility and increasing junction capacitances.